The present invention relates generally to Direct Memory Access (DMA) circuits in computing systems, and in particular to a DMA that terminates data transfers in response to value(s) of the data being transferred.
Modern computing systems—including those in portable electronic devices—process massive amounts of data, such as digital data representing photographs, graphic images, video, audio, and the like. This data must be transferred within the computing system, such as from an Input/Output (I/O) peripheral device into memory, from memory into a graphic frame buffer, from one area of memory to another—in general, from a data source to a data destination. A known technique to accomplish intra-system data transfer without burdening a processor is to include a Direct Memory Access (DMA) circuit, also known as a DMA controller.
A processor initializes the DMA controller with source and destination information (either of which may comprise memory addresses or peripheral ports) and a transfer count, such as by writing the information to control registers in the DMA controller, or by writing control blocks in memory and placing a pointer to them in a DMA controller register. Upon receiving a GO indication or command from the processor, the DMA controller autonomously reads data from the source and writes it to the destination, repeating the process until the specified number of data units has been transferred. Sophisticated DMA controllers may include multiple channels, and may handle many low-level data transfer tasks, such as scatter/gather operations to transfer data between units having different word sizes. It is also known to chain DMA transfers. In chained operations, the DMA controller is provided or directed to information for a subsequent DMA transfer (e.g., a new source, destination, count, and the like), which it begins upon termination of an ongoing DMA transfer.
The processor cannot always know a priori the length of a collection of data requiring a transfer within the computing system. For example, to copy a character string (such as “Hello world”), each character is retrieved from a source location, placed in a register, and compared to zero (the C language string termination character). If the comparison fails, the character is written to a destination location and the next character is read and compared. The data transfer is complete when the processor encounters a zero in the character string. This is a processor-intensive task, and additionally one that includes a very large number of memory accesses. If the source and/or destination addresses are non-cacheable, the CPU may spend considerable time waiting for the memory operations to complete, particularly in systems where memory accesses are much slower than processor execution. This severely degrades processor performance.
The data transfer task is generally not off-loaded to a conventional DMA controller, since the length of the character string is unknown. Conventional DMA controllers have no ability to inspect the data they transfer, and “blindly” transfer a specified amount of data from a source to a destination. The length of a character string is determined by comparing each character to a known data pattern. This comparison is conventionally performed by a processor. For the processor to off-load the data transfer task to a conventional DMA controller, it would have to successively read and compare characters to determine the string length, and then formulate a DMA operation, with a transfer count. However, since doing so performs half of the data transfer task (reading), processors in systems with conventional DMA controllers simply write each character to the destination directly, and halt the process when the known data pattern demarking the end of the string is detected.
Other protocols terminate data strings with multiple characters. For example, in the Hyper-Text Markup Language (HTML), a string to receive certain formatting or handling is terminated by the sequence </keyword>, which requires a plurality of successive character comparisons to detect.